View AN2846_8357755.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

february 2010 doc id 15130 rev 1 1/35 AN2846 application note sclt3-8 - guidelines for use in in dustrial automation applications introduction the serial current limited termination device sclt3-8 provides 8 inputs and supports the data transfer of the input states through a limited opto-transistor count thanks to the digital spi (serial peripheral interface). the purpose of this document is to: help designers to use the sclt3-8 in basic operations and to allow them to use it easily in their own applications by describing the sclt3-8 behavior in detail (refer also to the sclt3-8 device datasheet and to the user guide for the evaluation board steval-ifp000v1.) provide basic schematic diagrams provide information on the thermal behavior of the sclt3-8 device offer recommendations to achieve robust sclt 3-8 designs to optimize emi protection in accordance with industry standards (iec 61000-4-2, 4-4, 4-5 and 4-6) www.st.com
contents AN2846 2/35 doc id 15130 rev 1 contents 1 application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 features of the sclt3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 current-limited inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 maximum input current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 input characteristics (iec 61131-2 standard) . . . . . . . . . . . . . . . . . . . . . 6 1.2.3 digital input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.4 input signal frequency limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.5 input state monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 monitoring functions and regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.1 vcc monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.2 power loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.3 overtemperature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.4 internal voltage regulator 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 input state register and parity bit generator . . . . . . . . . . . . . . . . . . . . . 14 1.4.2 data shift register and control shift register . . . . . . . . . . . . . . . . . . . . . . 15 1.4.3 digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 spi functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.5 spi timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 thermal dissipation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 forward inputs polarity case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 reverse polarity on a single input case . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 temperature gradient on the sclt3 and on the board . . . . . . . . . . . . . . 20 3 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 basic sclt3-8 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 component definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 isolation management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 opto-coupler isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 magnetic digital isolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AN2846 contents doc id 15130 rev 1 3/35 5 sclt3-8 link configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 electromagnetic compatibilit y (emc) requirements . . . . . . . . . . . . . . 29 6.1 iec 61000 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 iec 61000 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 iec 61000 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 results on input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.2 results on vc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 iec 61000 4-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
application guidelines AN2846 4/35 doc id 15130 rev 1 1 application guidelines 1.1 features of the sclt3-8 the sclt is an octal input active termination device designed for 24 v dc high density input modules used in industrial automation. each channel circuit terminates the connection between a high side proximity sensor and the i/o module. the advanced features of the sclt3-8 comp ared to the basic clt3-4bt6 device are: spi for digital output count reduction doubling of input terminations: 8 inputs compared to 4 input state monitoring by leds from the process section undervoltage alarm detection of the power bus power bus loss detection 5 v supply source available for external driving circuits like opto-couplers or magnetic isolators overtemperature detection checksum data transmission through spi for better data transfer integrity the sclt3-8 also features an input overvoltage protection. this input protection makes this device robust against electromagnetic interference as defined in iec 61000-4-x standards: esd, fast transient bursts, and voltage surges. it is housed in a very low r th exposed pad, surface mount, htss0p38 package to reduce the circuit board size and the cooling pad. figure 1 shows the schematic block diagram for the device. figure 1. schematic block diagram v cs v dd input state register data transfer logic transfer logic shift register parity bits gen. 4 lines 8 lines 8 lines 8 lines prog. digital filters 8 lines current reference oscillator undervoltage alarm power reset power supply /cs spm sck mosi /miso com s miso v c dvr osc ref in 1 ld 1 in 8 ld 8 com p v dd overtemperature alarm write v dd shift ctrl shift register 8/16 bits bits shift input protection and input current limiters mosi
AN2846 application guidelines doc id 15130 rev 1 5/35 the sclt3-8 has been designed to run with spi protocol c pha = 0 and c pol = 0. the frame format is 16 bits or 8 bits long according to spm pin level. when spm is grounded, 16 bits are transmitted - 8 input data bits and 8 control bits. when spm is connected to v dd only the 8 input data bits are transmitted. ta bl e 1 defines the significance of the16 bits. bit 15 is the most significant bit. detailed spi functionality is described in section 1.4 . 1.2 current-limited inputs 1.2.1 maximum input current setting all internal bias currents sources and particularly the input current limiter are defined by the reference resistor connected to pin ref. a 15 k resistor will assure a typical input limited current of 2.35 ma (see figure 2 ). the typical limited input current i lim is given by the formula: figure 2. current limiter diagram the technology used allows a very low current dispersion according to the different channels (less than 10%). the reference voltage v bg is also compensated over the junction temperature range from -25 c to 150 c enab ling a good stability of the limited current (see figure 3 ). table 1. 16-bit frame definition data bits bit15 bit14 bit13 bit12 bit11 bit10 bit09 bit08 in 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 control bits bit07 bit06 bit05 bit04 bit03 bit02 bit01 bit00 /uva /ota pc1 pc2 pc3 pc4 0 1 () v k r v i ref bg lim 25 . 1 v cal with typi 5 . 1 30 bg = + = led_on 1 : 20 r ref =15k ref 2 : 3 1 : 1 1.5k led i lim coms v bg =1.25v
application guidelines AN2846 6/35 doc id 15130 rev 1 figure 3. limited current versus junction temperature figure 4 shows the i lim trend versus r ref . according to the input current setting and therefore the dissipated power, the sclt3-8 should be cooled with a sufficient copper heat sink area (see section 2 ) figure 4. typical limiting input current versus r ref 1.2.2 input characteris tics (iec 61131-2 standard) according to the iec 61131-2 standard and referring to type 3, when the input current is less than 1.5 ma the output circuit passes all the input current, keeping the monitoring led off and transmits a low level state to the input state register. when the module input voltage v i , taking into account the 2.2 k input resistor, is higher than 11 v (that is, the sclt3-8 input voltage v in is higher than 5 v) the monitoring led is on and the circuit transmits a high level state to the input state register. figure 5 gives the input characteristics and operating regions of type 3, defined in the iec 61131-2 standard, and the typical sclt3-8 input characteristic. vcc = 24 v, vi = 11 v 2.1 2.2 2.3 2.4 2.5 2.6 -25c 25c 125c 150c i (ma) lim junction temp (c) in1 in2 in3 in4 in5 in6 in7 in8 2.0 3.0 4.0 5.0 6.0 7.0 8.0 3 5 7 9 11 13 15 15 9.1 3.9 i (ma) lim test conditions: i versus r v = 24 v, v = 24 v lim ref cc i r (k) ref
AN2846 application guidelines doc id 15130 rev 1 7/35 figure 5. input characteristic according to iec 61131-2 type 3 current limited inputs allow reduced power dissipation into the device as well as reduced power needed by the external supplies. a typi cal application circuit schematic is shown in figure 31 in the application section. figure 6 displays the sclt3-8 input stage configuration and its typical input threshold voltages. low frequency triangular waveform as the input voltage has been used to better highlight the voltage thresholds. input current (i in ) and voltage across the leds are also displayed in figure 6 . the v led wave shape shows clearly the on-off states of the sclt3-8. figure 6. input stage with r in = 2.2 k , t he typical v i_on and v i_off threshold voltages are respectively 9.5 v and 8.5 v, consistent with the 11 v min. and 5 v max specified in the iec 61131-2 standard. the hysteresis (1 v) improves the input noise immunity. the module input thresholds are the results of drop voltage across the input resistor r in , into which flows t he input current i in , and the sclt3-8 input thresholds v th_on and v th_off . the input current limiter is activated typically when v in = 3.7 v, before the v th_on threshold is reached. in all cases the following formula can be applied: when the input current limiter is activated, the formula becomes: the typical module input threshold voltage can be calculated as follow: 11v 5v i in (ma) 2.0 1.5 v in (v ) on off on 0.1 11v 5v on region off region transition region sclt3-8 (including r in ) input characteristic i limit off off led r in 2.35 ma v i input status v th i in v in digital filter v in : 2v/div v i : 2v/div i in : 1ma/div v led v in_on = 9.5 v v in_off =8.0 v i lim = 2.35 ma input stage configuration typical input voltage thresholds in in in i v i r v+ = in ilim in i v i r v+ = math composer 1.1.5 on vth ilim in on in v i r v _ _ + =
application guidelines AN2846 8/35 doc id 15130 rev 1 the proposed r in value of 2.2 k has been calculated to meet the iec 61131-2 threshold requirements. users can set their own particular application threshold voltages by applying, in the formula given above, the v in they want to achieve and find the corresponding r in value. take note, the higher the r in , the better will be the immuni ty against voltage surges. a particular useful application is when an input type 2 is needed. figure 7 shows the solution of connecting r in7 and input r in8 = 1.5 k in parallel and tuning the i lim with r ref = 9.1 k to get 3.5 ma (see figure 4 ) in each input branch . of course corresponding bits (b14, b15) will be set togethe r at the right stat e according to the level applied at the common input. unused led outputs must be grounded to maintain the flow of the current in its corresponding chanel. figure 7. in 7 and in 8 parallel wired for type 2 the different threshold voltages and the i limit = 7.0 ma are shown in figure 8 below. figure 8. threshold voltages - type 2 configuration using two inputs in parallel r ref = 9.1k r in = 1.5k type 3 inputs type 2 inputs in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 led 2 led 1 led 5 led 6 led 7 led 8 led 4 r ref led 3 v i (2v/div) v in (2v/div) i in (5ma/div) v led v i_off = 8.4 v v i_on = 9.9 v i limit = 7.0ma
AN2846 application guidelines doc id 15130 rev 1 9/35 1.2.3 digital input filter input parasitic disturbances can be removed by the programmable input digital filter. it is based on an rc oscillator, a divide r and a two step filter (see figure 9 ). figure 9. digital input filter. the internal capacitor value is typically 10 pf. the oscillator resistor is connected externally on pin r osc . the clock divider is set at 8 when the pin dvr is connected to gnd or at 64 when it is connected to v dd . the two step filter validates the input voltage when it sees at least three rising edges as shown in figure 9 . the delay time is between 2 t osc and 3t osc . a wide filter time range, t ft , can be set by using the couple r osc and dvr as shown in below in figure 10 . figure 10. minimum t ft versus r osc the user can also choose a particular typical filter time, t ft , by calculating the corresponding r osc value from the formula: oscillator ref1v divider filter_2step oscr dvr in<1:8> out<1:8> osc ckf por osc period = 1.2 s r osc = 51 k dvr=8 0 100 200 300 400 500 600 0 500 1000 1500 rosc(k ) dvr=64 0 1000 2000 3000 4000 0 500 1000 1500 rosc (k ) t (s) ft t (s) ft math composer 1.1.5 12 ft 10 5 . 23 1 1 2 t - = dvr r osc
application guidelines AN2846 10/35 doc id 15130 rev 1 1.2.4 input signal frequency limitation the maximum frequency transmitted trough the current limited inputs is limited by 3 factors: 1. the input digital filter, which cuts undesirable frequencies. r osc set to 51 k and dvr connected to gnd ensures that the input signal has to be at a stable level for more than 20 s to be taken into account. this allows a maximum input frequency of 25 khz. it can be reduced to 130 hz using the combination of r osc = 1.5 m and dvr connected to v dd . 2. the input capacitors c in are used to increase the emi immunity filter of the input signal. r in = 2.2 k and c in = 22 nf ensures a 3.2 khz low pass filter. 3. the spi sampling effect - the input states are taken into account at each /cs fall (see section 1.4.4 ). this achieves a sampling of inputs at the /cs frequency, as shown in figure 11 . the input states will be correctly tran smitted if the samp ling mode meets the shannon equation: figure 11. sampling effect as the /cs period is dependant on the frame length, ta bl e 2 below gives some useful combinations of sck frequency signal, frame length and current limited input frequency. frequency input max f with period signal /cs the t with : t 1 f with f 2 f input /cs /cs /cs input cs / = = ? = t input /cs current limited input signal low level capture missed high level capture missed t /cs table 2. input frequency versus sck and length frame f sck 0.1 1.0 2.0 mhz frame length 8 16 32 64 8 16 32 64 8 16 32 64 bits t /cs 80 160 320 640 8 16 32 64 4 8 16 32 s f current limited input 6.25 3.125 1.56 0.78 62.5 31.25 15.6 7.8 125 62.5 31.25 15.6 khz
AN2846 application guidelines doc id 15130 rev 1 11/35 1.2.5 input state monitoring the state of each of the 8 monitoring leds is an image of the 8 filtered input states. all the monitoring led cathodes have to be connected to ground. in the on state a current of i lim reduced by 0.15 ma is available for each led. in case of a led not being used, the led output pin must be connected to the ground com p to allow the input current to flow back to the ground. the leds must be chosen with a v f voltage less then 2.7 v (at minimum operating temperature -25 c). 1.3 monitoring func tions and regulator 1.3.1 v cc monitoring the power bus voltage connected to v cc is sensed by the v cs pin through a resistor bridge. the v cs threshold voltage is typically 1.25 v with a hysteresis of 100 mv. designers can easily set their own alarm detection voltage by an appropriate resistor bridge (see figure 12 ) using the formula: figure 12. uva comparator for example, the resistor bridge consisting of r s = 1.5 m and r pd = 120 k produces uva activation when v cc drops below 17 v. the uva activation has no effect on sclt3-8 behavior but the information is transmitted trough the spi bus by setting bit 7 to low state in the control bits register (see figure 13 and figure 14 ). to eliminate any short voltage disturbances that could trigger the uva, a 1 ms delay circuit has been inserted in the output line of the uva comparator. ) 1 ( min _ pd s cs cc r r v v+ = r s r pd v bg =1.25v v dd v cc 1ms delay uva v cs com
application guidelines AN2846 12/35 doc id 15130 rev 1 1.3.2 power loss detection for a greater voltage drop on v c , a power supply loss detection has been added. this immediately sets miso output at low level state when v c is below 8 v, as shown in figure 15 and figure 16 . the mcu can then interpret that if all bits are equal to 0, this means that v c is too low. 1.3.3 overtemperature detection when the junction temperature exceeds 150 c an overtemperature alarm sets the miso bit 6 at low state in the control bits register. the sclt3-8 remains operational. the mcu receiving the alarm has to take the correcti ve actions. the alarm w ill be reset when the junction temperature falls below 135 c. 1.3.4 internal voltage regulator 5 v the input of this voltage regulator is internally connected to the v c pin. the voltage regulator supplies the digital part of the sclt3-8 and therefore it defines the high digital level. it also supplies the sourced current available at pin miso. it can also supply application needs (such as opto-coupler s and micro transformers) through pin v dd . its total current capability is 9 ma for a 3% voltage drop on v dd (see figure 17 ). figure 13. v cc = 24 v, uva bit not activated figure 14. v cc = 16 v, uva bit activated v cc = 24 v miso sck /cs miso sck /cs v cc = 16 v miso sck /cs miso sck /cs figure 15. communication stops for v c < 8 v figure 16. communication resumes for v c > 8.1 v v c 8.0 v miso goes to l /cs sck miso 8.1 v /cs sck miso
AN2846 application guidelines doc id 15130 rev 1 13/35 figure 17. regulator output voltage figure 18 shows the schematic diagram of a solution for applications where greater current is needed. the bypass transistor allows extra current while maintaining a 5 v regulated voltage (see figure 19 ). the proposed circuit allows a 25 ma current load capability with a v dd regulation <2%. an additional input protection device, like smaj30a, is needed to comply with voltage surges because r c has to be reduced to limit the voltage drop across it. the dissipated power in the bypass transistor pzt2n2907a is 550 mw. components used: pzt2n2907a (sot223 with 1 cm 2 copper area) r c = 330 ( 1/8 w) , r e = 51 ( 1/8 w) 1.4 spi functional description three registers (refer to figure 1 ) are used to transfer input data and control data to the 16-bit data frame. the data frames are transmitted through four interface signals: /cs, sck, mosi, and miso. 4.5 4.6 4.7 4.8 4.9 5.0 5.1 v -3% dd 9.0 v (v) dd i (ma) dd v versus i dd dd figure 18. v dd booster schematic figure 19. load regulation with v dd booster r e r c v cc 2n2907a i dd v v dd i rc smaj30a sclt3 in 1 in 2 in 3 in 4 v c v dd led 2 led 3 led 1 r ref v cs 0.00 5.00 10.00 15.00 20.00 25.00 4.800 4.850 4.900 4.950 5.000 5.050 5.100 0.00 5.00 10.00 15.00 20.00 25.00 i (ma) dd v (v) dd v dd
application guidelines AN2846 14/35 doc id 15130 rev 1 1.4.1 input state register and parity bit generator after filtering, the 8 input termination states are stored in an 8-bit input state register. its content is an image of the filtered input states in real time. figure 20. input state register and parity bit generator. the sclt3-8 has been designed to help diagnose incorrect data transmission. the four parity bits generated by the parity bit generator are computed according to the input states register content. they are updated each time the input state register content changes. the parity bit 5 of pc1 register controls the 1 to 8 input data states; pc2-bit 4 controls inputs 5 to 8: pc3-bit 3 controls inputs 1 to 4;pc4-bit 2 controls inputs 3 to 6 according to the logic equation:. see example in figure 21 . the decoding of all the parity bit results will help the microcontrolle r detect the possible corrupted pair of bits occurring during the transmission. figure 21. parity bit generation example. 8 lines input state register parity bits gen. filtered input states http://www.mathcomposer.com . , inputstate 1n8 1n7 1n6 1n5 1n4 1n3 1n2 1n1 1 0 0 1 1 0 0 1 pc1 pc2 pc3 pc4 1 2 3 4 from input state filter from input state filter input state register 8 lines 8 lines parity bbits gen.
AN2846 application guidelines doc id 15130 rev 1 15/35 1.4.2 data shift register and control shift register data and control shift re gisters are each 8 bits long. at ea ch /cs falling edge all the data is frozen and the 8 bits of the input states register are transferred to the data shift register (bits 8 to 15) while the control bits, consisting of four parity bits, overtemperature alarm bit, undervoltage alarm bit and the stop bit, are transferred to the control shift register (bit 0 to 7). the two last bits (bit 1 and bit 0) are always se t respectively to 0 and 1 indicating the end of data frame except in power loss case where all bits are set to 0. bit 15 will be the msb and bit 0 the lsb. figure 22. data and control data shift registers. 1.4.3 digital inputs and outputs these digital pins are involved with the spi: /cs: chip select input sck: serial clock input miso: master-in slave-out output /miso: complementary miso state mosi: master-out slave-in input (connected to ground when not used) to improve the immunity of the digital inputs ag ainst noise, the digital inputs /cs, sck and mosi have been designed to use a schmitt trigger configuration. each input is connected to v dd through a high impedance pull up resistor to set the input at high level state when no input signal is applied. protection diodes are inserted with these pull-up resistors to prevent the esd reaching the v dd . the digital input diagram is given in figure 23 . input state register parity bits gen. data shift register control shift register overtemperature alarm undervoltage alarm 4 lines 8 lines 8 lines
application guidelines AN2846 16/35 doc id 15130 rev 1 figure 23. digital inputs diagram. the digital output signal miso is delivered through a high-z impedance buffer able to source or sink 3 ma. figure 24. digital output mosi /cs sck mosi v dd com s v dd en uva m1 m2 mosi com com s
AN2846 application guidelines doc id 15130 rev 1 17/35 1.4.4 spi functionality at the /cs falling edge the fo llowing operations are done: the input data states, parity and control bits are frozen and stored in the data and control shift registers. the msb (bit 15) is shifted out first to miso. the sclt3-8 data transfer uses spi protocol with c pol = 0, c pha = 0 conditions. this means the sck signal must be at low level state when the /cs is falling (communication starts). in this case the msb (bit15) is transferred first from miso as soon as /cs falls, and all the remaining bits are transferre d at each sck falling edge. figure 25. sck and /cs synchronization security for more flexibility the spi protocol has been enhanced and takes into account the case where sck signal is at high level when /cs falls to low level. in this case, as previously the msb will be present at miso pin at the /cs fa lling edge but the following bit will be available only at the second sck falling edge. in both cases the rule is: a rising sck edge must occur after the falling /cs edge to validate the first sck falling edge. otherwise the state change duration of miso may be too short to correctly trigger the transmission of the msb (bit 15) (see figure 25 ). in normal operation the two last bits are 0 and 1 indicating the end of the transmission. the data transmission runs as long as the /cs is at low state. as soon as /cs returns to high level, the data transfer is disabled and the miso output is in high impedance - hi-z. when mosi input is used in daisy chain operation, the inputs are captured at each sck rising edge and loaded into the shift register. loaded data has no effect on the sclt3-8. figure 26. 16-bit transmission example miso /cs sck miso /cs sck bit14 miso /cs sck bit14 sck is low when /cs falls sck is high when /cs falls /cs sck miso b15 b8 b7 b0 input data bits control bits 10 1 0 1111111 011 01 10 1 0 1111111 011 01
application guidelines AN2846 18/35 doc id 15130 rev 1 figure 26 shows a 16-bit transmission example when the application is running in good conditions: application is correctly supplied: /uva, bit 7 not activated sclt3-8 junction temperature less than 150 c: /ota, bit 6 not activated correct transmission: parity bits in accordance with input states 1.4.5 spi timing definition the four spi signals involved: /cs, sck, mosi, miso are described in figure 27 . a fifth /miso pin output signal is also present. the typical sck frequency is 1 mhz, but the sclt3 can run at up to 2 mhz. the other more important timing parameters are: t d : delay time. this is the delay time of miso between sck falling edge and miso change. t s : set up time. this is the minimum holding time of mosi input data for its capture before the sck rising edge. t h : holding time. this is the minimum holding time of mosi input data after the sck rising edge for its correct capture. the most important rules to meet to perform a correct data transmission are: t cl > t d + t s t ch > t h . figure 27. spi timing definition. t ld t ch t hc t a t dis /cs miso mosi sck msb s lsb s msb m t c t d t dt 12 16 t s t h t cl
AN2846 thermal dissipation calculation doc id 15130 rev 1 19/35 2 thermal dissipation calculation 2.1 forward inputs polarity case in reference to the application schematic defined in figure 31 , the dissipated power into the sclt3-8 p sclt can be calculated as following: consider the worst case where all inputs are connected to 30 v. p sclt = p1 - p2 where: p1 is the total power delivered by the supplies p2 is the total power dissipated by the external components p1 = v cc (i c + i dd + 8 i lim ) external components are: r in , r c , leds, regulator load power dissipated by input resistors = 8 r in i lim 2 power dissipated by supply resistor = r c (i c + i dd )2 power dissipated by leds = 8 v led i led power supplied by the v dd linear regulator = v reg i dd the p sclt = 560 mw assuming: v cc = 30 v, i lim = 2.35 ma, r in = 2.2 k , r c = 1.0 k , v led = 2 v, v dd = 5 v, i dd = 7ma. note: the current flowing through the led is almost the same as i limit . the difference is about 125 a used to bias the input circuit device. with the above mentioned conditions and using copper area of 1cm 2 as heat sink, the sclt3-8 junction temperature will be around 120 c with an ambient temperature of 85 c. figure 28 below shows the r th_ja variations versus the heat sink area on a 35 m fr4 epoxy single side board. figure 28. r th_ja versus copper area htssop38 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 r (c/w) th(j-a) sclt s (mm2) cu
thermal dissipation calculation AN2846 20/35 doc id 15130 rev 1 2.2 reverse polarity on a single input case each input resistor can be connected to a reverse polarity down to -30 v. this case corresponds to a connection mistake or a reverse biasing that is generated by the demagnetization of a monitored inductive solenoid. the involved input can withstand a high reverse current up to 20 ma. the corresponding state transmitted is low level. the other inputs remain operational. the power dissipated into a reverse polarized input is low, but attention has to be paid to power dissipation into the inpu t resistor which sustains almost all the reverse voltage. 2.3 temperature gradient on the sclt3 and on the board figure 29 shows the case top temperature when sclt3-8 dissipates 600 mw, which corresponds to maximum supply case with v cc and all module inputs at 32 v. the heat sink is 100 mm 2 , and the ambient temperature is 25 c. in this example the maximum case top temperature reaches 68 c. the case top temperature is a good indication of the junction temperature, which can be estimated using thermal analysis techniques. figure 29. case top temperature () = - = = - = k 2.2 r and v for mw 390 in in v p dis_rin r v p dis_rin in i 30 7 . 0 2 r = 1.1 k r = 2.2 k lens: g1 (board paint in black) c in
AN2846 thermal dissipation calculation doc id 15130 rev 1 21/35 figure 30 shows the temperature gradient of the sclt3-8 board with the same supply conditions as above. almost the totality of the power is concentrated around the sclt3-8 and its heatsink. no particular temperature hot spot can be detected on the board. figure 30. temperature gradient of the board profil 1 profil 1 profil 1 profil 1
application circuit AN2846 22/35 doc id 15130 rev 1 3 application circuit 3.1 basic sclt3-8 board description the basic electrical schematic diagram using a single sclt3-8 fulf ills the requirements defined in the iec 6131-2 standard. it is easy to duplicate this configuration to meet more complex applications using many inputs and several sclt3-8s. the major settings are: type 3 configuration 16-bit frame (spm grounded) 16 s digital input filtering (r osc = 51 k , dvr grounded) figure 31. type 3 application diagram 15k 2.2k in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 led 2 led 1 led 5 led 6 led 7 led 8 led 4 r ref led 3 dvr osc spm com p v c v cs com p com p com p com s v dd /cs sck mosi /miso miso 51k 1.0k 1.5m 120k 33n 33n sclt3-8 470p 470p 220 220 j1 j2 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 22n 22n 22n 22n 22n 22n 22n 10n 10n
AN2846 application circuit doc id 15130 rev 1 23/35 3.2 component definitions the reference resistor r ref tolerance gives the accuracy of the input limiters. 1% accuracy is suggested. the typical type 3 sclt3-8 application uses r ref = 15 k and r in = 2.2 k . type 2 can be also achieved as shown in ta bl e 3 . the input melf resistors are used to sustain high voltages occurring during surge tests. using type 2, the power dissipated by the sclt3-8 reaches 1w with v i = v cc = 24 v. a copper heat sink area of 1 cm 2 will set t j at 150 c with an ambient temperature of 65 c. the r c value has to be chosen with attention. the voltage drop across this resistor is the product of sclt3-8 supply current and any load current supplied by vdd: regulator output current and sourced miso current. the resulting voltage v c must be in any case above the 8 v activation threshold to avoid a spurious power loss detection. 1 k meets this requirement and allows 2 kv of voltage surge. the 22 nf input capacitors are used to impr ove the noise immunity of the whole module. their function is to filter the high frequency elec trical noise, and to secure the off state of the module. adding a 33 nf capacitor on v c pin ensures high immunity agai nst electrical noise such as that described in the iec 61131-2 standard. r osc = 51 k and pin dvr grounded set the input digital filter to eliminate pulse widths below 20 s. a 33 nf capacitor connected on v dd output ensures a good output of the voltage regulator. the leds must be chosen according to their input diode drop voltage. led outputs can drive leds with forward voltage up to 2.7 v. low pass rc filters have been inserted into digital inputs /cs and sck to improve the immunity against fast transient bursts. r = 220 and c = 470 pf give a good compromise between immunity result and sclt-3 speed which can run up to 1 mhz. table 3. type 2 and 3 configurations type 3 type 2 unit r ref 15 3.9 k r in 2.2 0.75 k typical i limit 2.3 6.5 ma
application circuit AN2846 24/35 doc id 15130 rev 1 3.2.1 footprint the footprint given in figure 32 allows ground connection optimization of com p and comp s . the 1 cm 2 heat sink area defines an r th-ja of 80 c/w. figure 32. foot print (not to scale) 6.10 8.80 3.50 0.6 11.35 1.35 3.425 1.30 2.575 0.4 0.25 5.00 0.65 pin 1 package footprint additional copper for extra-cooling 0.6 s copper = 100 mm 2 copper thickness : 35 m
AN2846 isolation management doc id 15130 rev 1 25/35 4 isolation management there are two solutions proposed for galvanic isolation between the sclt3-8 and the microcontroller. opto-coupler isolation magnetic digital isolation 4.1 opto-coupler isolation the first solution is given by opto-couplers which must run at a bit rate compatible with the sck frequency and meet sclt3-8 requirements in terms of consumption. hcpl4506 or hcpl0466 can be a solution to drive a single sclt3-8 for a 1 mhz application. figure 33. single sclt3-8 and hcpl4506 or 0466 if several sclt3-8s are used, more current is available through v dd pins to supply the opto- couplers. the different outputs v dd can be tied together but, low serial resistors (22 ) must be inserted to balance the different regulated output voltages. the load current is shared between the two sclt3s and allows th e voltage drop reduction across each r c resistor. v c sck /cs /miso mosi miso v cc miso /cs sck 3 k 3k 3k 1 k 750 750 hcpl4506 or 0466 v dd v dd2
isolation management AN2846 26/35 doc id 15130 rev 1 figure 34 shows two sclt3s in daisy chain co nfiguration using acpl-k73l (dual) and acpl-w70l (single). figure 34. two daisy-chained sclt3-8s and acpl/k73l/w70l v dd2 /cs sck miso 1 k 750 22 22 acpl-k73l acpl-w70l v sck /cs /miso mosi miso v v v c sck /cs /miso mosi miso v cc v dd v sck /cs /miso mosi miso v v v c sck /cs /miso mosi miso v cc v dd 750 hcplk73l hcpw70l
AN2846 isolation management doc id 15130 rev 1 27/35 4.2 magnetic digital isolator the second solution is given by digital isol ators. the triple-channel digital isolator adum1301 is convenient for such an sclt 3-8 application. the sending channels v ia and v ib are used for /cs and sck signals while receiving channel v ic is used for miso signal. the v dd pin of sclt3-8 can easily deliver th e typical supply current needed by v dd2 , which is around 2.7 ma at 2 mhz as shown in figure 35 . figure 35. digital isolator sclt3 - 8 v c sck /cs /miso mosi miso v v dd sclt3 - 8 v sck /cs /miso mosi miso v cc v 2 gnd gnd 2 voa vob vic nc ve 2 adum1301 1 gnd vib voc nc ve 1 gnd 1 2 1 via v dd v dd
sclt3-8 link configurations AN2846 28/35 doc id 15130 rev 1 5 sclt3-8 link configurations parallel and daisy chain configurations can be implemented using sclt3-8 or other devices compatible with a serial peripheral interface. in parallel mode the microcontr oller selects the sclt-8 with wh ich it wants to communicate by setting the corresponding /cs to low state as long as the communication lasts. the microcontroller should be able to control as many /cs pins as sclt-8s it wants to address. while in daisy chain configuration the microcontroller commands at the same time all the sclt3-8s connected in series. the data must transit from sclt3-8 to sclt3-8 going out from the miso pin, going in through mosi pin till reaching the last one connected to the microcontroller. considering n sclt3-8s conne cted in daisy chain, the microcontroller has to read n times 16 bits and the communication time is proportional to n times 16 bits. figure 36. daisy-chain configuration figure 37. parallel configuration sck miso /cs mosi sclt 1 sck miso /cs mosi sclt 2 sck miso /cs mosi master spi sclt 1 sck miso /cs1 mosi master spi sck miso /cs1 mosi sclt 2 sck miso /cs2 mosi /cs2
AN2846 electromagnetic compatibility (emc) requirements doc id 15130 rev 1 29/35 6 electromagnetic compatibility (emc) requirements the sclt3-8 has been designed to withstand electromagnetic interference as specified in the iec 61131-2 standard. this international standard gives all the requirements and conditions for tests that must be performed on the programmable logic controllers (plc) and their associated peripherals. iec 61000 4-2, 4-4, 4-5 and 4-6 standards define test methods. the current limited inputs and supply pins of sclt3-8 are protected against high voltage disturbances by a clamping circuits that are grounded to the common pin com p . combined with serial input resistances r in or r c (see figure 38 ). these clamping circuits are effective against esd (8 kv contact), fast transient burt (2.5 kv), and voltage surge (1 kv). figure 38. protection clamping circuits 6.1 iec 61000 4-2 this standard specifies the behavior of the device when subjected to electrostatic discharges. the discharges must be applied to operator accessible parts. this means that these tests have to be performed on each connector pin. the required levels are: air discharge: 15 kv, contact discharge: 8 kv. the system must continue to operate as intended after the discharge. temporary degradation of the performance is acceptable during the test, but the system must recover by itself after the test (b criterion). all sclt3-8 pins are esd protected. com p com s v c 39v supply circuit v cc com p com s input circuit in 1 39v in 2 39v in 3 39v in 4 39v in 5 39v in 6 39v in 7 39v in 8 39v r in
electromagnetic compatibility (emc) requirements AN2846 30/35 doc id 15130 rev 1 6.2 iec 61000 4-4 this standard specifies the behavior of the device when subjected to a fast transient burst. the fast transient burst must be applied on all the input pins of the system. a capacitive clamp-coupling device is used as described in the iec 61000-4-4 standard. the required sustainable burst voltage level is 2.5 kv. the system must continue to operate as intended. no temporary degradation of the performance is acceptable during the test (a criterion). new test methodology has been set up to chec k the frame integrity against fast transient bursts. the need to monitor each bit level leads to using a scope isolated from the test bench through optic fibers. the generation of /cs and sck input signals are also isolated through the same way as shown in figure 39 . current and voltage level adaptation is done through an optical fiber interface (ofi). long frames history can be stored in the monitoring scope for an easier detection of disrupted bits. the sclt3-8 immunity has been increased by adding rc filter networks connected on /cs and sck input pins. but these rc filters act as low pass filters and limit the maxim data transfer speed. for example the filter made of r = 220 , c = 470 pf allows a 1 mhz transmission frequency and ensures device ftb immunity up to 4 kv. the test configuration is shown in figure 39 . figure 39. two supplies configuration table 4. speed - ftb immunity compromise rc values sck speed ftb immunity 220 - 220 p f 2 mhz 3 kv 220 ? 470 pf 1 mhz 4 kv generator capacitive clamp sclt3-8 ofi /cs miso sck ofi /cs miso sck /cs miso sck scope fiber optic cable ftb generator bat 1 bat 2
AN2846 electromagnetic compatibility (emc) requirements doc id 15130 rev 1 31/35 figure 40 shows the output miso behavior is not disturbed during fast transient bursts. the ftb signal has been captured through an antenna to observe where the bursts act. figure 40. output miso behavior during fast transient bursts figure 41. test bench ftb 200 s = 5 khz = cs miso /sck ftb + 4.0 kv haefely ftb generator capacitive clamp ofi sclt3 board bat1 sclt3 inputs, gnd bat2 fiber optic cable
electromagnetic compatibility (emc) requirements AN2846 32/35 doc id 15130 rev 1 6.3 iec 61000 4-5 this standard specifies the behavior of the device when subjected to voltage surges applied on all input pins of the syst em. for all analog inputs, th e coupling method is a 42 serial resistance and a 0.5 f capacitor. for the dc power line, the coupling is 2 resistor, and 18 f capacitor. the required voltage surge levels are: 1 kv for the input pins with r in = 2.2 k , 2.5 kv for the pin v c when r c = 2.2 k or 1 kv when r c = 500 . the system must continue to operate as intended. temporary degradation of the performance is acceptable during the test, but the system must recover by itself after the test (b criterion). 6.3.1 results on input pins when a positive surge voltage of 1 kv is applied on the input resistor r in , the input active clamp protects the sclt3-8 input and limits the input voltage at 40 v. the input current reaches 0.45 a. when a negative voltage surge is applied the input diode is biased in forward mode and the current is 0.45 ma (see figure 42 ) figure 42. v in and i in behavior v surge 0.2kv/div + 1.0 kv v in i in 0.45a 0.2a/div 20v/div 40v v surge v c i c 0.45a 0.5kv/div 0.2a/div 1v/div 1v -1.0 kv positive voltage surge negative voltage surge
AN2846 electromagnetic compatibility (emc) requirements doc id 15130 rev 1 33/35 6.3.2 results on v c pin when a positive or negative surge voltage of 1 kv is applied on the supply resistor r c , the v c active clamp protects the sclt3-8 input and limits the input voltage at 40 v. the current reaches 0.45 a. the wave shapes are similar to the previous ones as shown in figure 43 . figure 43. v c behavior with r c = 2.2 k 6.4 iec 61000 4-6 this standard specifies the behavior of the device when subjected to conducted radio frequency interference in the range 150 khz to 80 mhz. the rf signal, 80% modulated by 1 khz sinusoidal waveform, is injected at the inputs i in and v cc through a coupling device network (cdn). the required leve l defined into iec 61131-2 is 3 v rms. with these stress conditions, the system must continue to operate with no loss of function (a criterion). the test configuration used is shown in figure 44 . figure 44. rf test configuration sclt3-8 meets iec 61000 4-6 and iec 61311-2 standards requirements. better immunity can be obtained by decoupling pin sck with a 470 pf capacitor. v surge v c i c +1kv 0.45a 40v 0.5kv/div 0.2a/div 20v/div v surge v c i c 0.45a - 0.5kv/div 0.2a/div 1v/div 1v -1kv -1kv positive voltage surge negative voltage surge cws500c v cc cdn-af2 in 1-8 v cc gnd dut scope reference plane -6 db vi
conclusion AN2846 34/35 doc id 15130 rev 1 7 conclusion this application note illustrate s how designers can maximize sclt3-8 performances in their applications especially in the fields of bu s controller interface co nfigurations, thermal behavior and emi robustness. they will find information that helps them to design new system boards while saving time. designed for digital i/o module in factory automation, the sclt3-8 is a low-loss emi-proof solution showing high usage flexibility. with the sclt3-8, designers will be able to develop highly integrated modules interfacing proximity sensors with the following benefits: reduced pin count saved space (only 3 isolation devices for spi) reduced dissipation no need for additional led supply common spi availability emi proof to illustrate its performances and advant ages, an evaluation boa rd steval-ifp000v1 using 2 sclt3-8s configured in daisy chain is available with an optimized layout. 8 revision history table 5. document revision history date revision changes 22-feb-2010 1 initial release.
AN2846 doc id 15130 rev 1 35/35 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of AN2846

	To Download AN2846 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .